| 摘要 |
In a refresh counter for an SDRAM, an internal bank select address for the test of the refresh counter has a predetermined state in a test mode to correspond to an external bank select address in a burst mode, so that the refresh counter can simply be tested in the test mode. The refresh counter comprises a first counter circuit 21 for outputting a least significant bit as the internal bank select address in the test mode in response to an address signal and a reset pulse signal. The address signal is generated in each automatic refresh cycle, and the reset pulse signal is generated when the present mode is set to the test mode by a mode register set command. The refresh counter further comprises n second counter circuits connected in series to the first counter circuit, for outputting n bits of a row address. Circuit details of the first counter 21 are described (Fig 5). |
