| 摘要 |
PURPOSE:To secure enough time for taking out a counted result and to prevent malfunction from being generated in a high-speed operation by providing first and second counting means to respectively count clock signals in the first and second level priods of an applied data signal. CONSTITUTION:Since an output signal 3Q generated from a shift register 28 and the inverse of the 3Q are inverted each other, H and L counters 23 and 24 are alternately operated. The two counters 23 and 24 are provided to respectively detect the time lengths of H and L levels for a regenerative signal PBSG. As the result, the counters can be alternately operated, and signal (e) and (f) data of the counted results are remained in the counters 23 and 24 while stopping the count operations. These data can be latched by latch circuits 25 and 26 with enough time. Therefore, even when the request of the high-speed operation, namely, the frequency of a master clock signal MCK is increased, enough time for latching data can be secured, and malfunction is prevented from being generated in the high-speed operation. |
