IMPROVED SEMICONDUCTOR MEMORY WITH ROW DECODER OUTPUTTING ROW SELECTING SIGNAL AND ITS CONTROLLING METHOD

摘要

In a semiconductor memory circuit 100 according to the present invention, a column decoder 103 outputs column selecting signals to column lines (CL), whose output part is formed of inverter (125). A driving potential to be supplied to the inverter is set lower than a power supply potential Vcc supplied from outside. With this arrangement, a timing at which a bit line is connected to a data bus is determined by an amplification rate of a potential on the bit line, thereby providing the semiconductor memory device which performs a high speed and reliable operation. <IMAGE>