| 摘要 |
According to this invention, a semiconductor memory device includes N M-port RAMs (where each of M and N is a positive integer of not less than two), a data input terminal, N x (M-1) read address terminals, a write address terminal, and N x (M-1) data output terminals. The N M-port RAMs are operated in synchronization with a common clock signal. The data input terminal commonly inputs write data to data input terminals of the M-port RAMs. The N x (M-1) read address terminals independently input read addresses to first to (M-1)th port address terminals of the M-port RAMs. The write address terminal commonly inputs a write address to Mth port address terminals of the M-port RAMs. The N x (M-1) data output terminals independently output read data from data output terminals of the M-port RAMs.
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