Multiported cache and systems

摘要

A cache memory is provided with a plurality of address ports and a corresponding plurality of tag ports for use with multiple pipes in a pipelined system. One of the address ports is dedicated to snooping and the remaining address ports provide concurrent access to the cache for references to one or more independent addresses respectively issued by one or more pipes. A tag port is provided for each of the address ports to provide concurrent hit/miss status for each address.