Signal deskewing system for synchronous logic circuit

摘要

A global clock signal is distributed from its source to each module of a distributed synchronous logic circuit via two separate transmission lines. Portions of the two transmission lines extending between the clock signal source and each module are of similar length but have dissimilar velocities of signal propagation. A resulting phase difference between corresponding pulses of the global clock signal arriving at each module via the two transmission lines is proportional to the length of the transmission lines, and is therefore proportional to the inherent clock signal delay in either transmission line. A deskewing circuit at each module further delays the global clock signal after it arrives at the module on a first of the two transmission lines to produce a local clock signal at the module. The deskewing circuit at each module detects the phase difference between global clock signal pulses arriving at the module on the two transmission lines to determine the inherent delay of the first transmission line and then adjusts the local clock delay so that the sum of the inherent delay and local clock delay equals a standard delay. With the standard delay the same for all modules, the local clock signals produced at all modules are in phase with one another.