发明名称 |
Graphics processor writing to shadow register at predetermined address simultaneously with writing to control register |
摘要 |
A computer graphics system includes a host computer and a graphics processor. The graphics processor includes a control register. When the graphics processor writes to the control register it simultaneously generates a predetermined address on a local address bus and supplies data on a local data bus identical to data to be written into the control register. A shadow register circuit connected to both the host computer and the graphics processor includes a shadow register and first and second address decoders. The first address decoder enables a write from a local data bus into the shadow register upon detection of the predetermined address. The second address decoder enables a read from the shadow register via a host data bus upon detection of the predetermined address on a host address bus. The shadow register optionally includes a message in plurality of bits and a message out plurality of bits, the first and second address decoders enabling message passing between the host computer and the graphics processor. The shadow register circuit optionally includes a host interrupt bit and a buffer circuit. The buffer circuit generates a host interrupt signal to the host computer if either the graphics processor generates a host interrupt signal or the host interrupt bit of the shadow register has a predetermined state.
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申请公布号 |
US5696923(A) |
申请公布日期 |
1997.12.09 |
申请号 |
US19950474863 |
申请日期 |
1995.06.07 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
ROBERTSON, IAIN C.;NYE, JEFFREY L.;ASAL, MICHAEL D.;SHORT, GRAHAM B.;SIMPSON, RICHARD D.;LITTLETON, JAMES G. |
分类号 |
G06F3/14;G06F9/30;G06F12/02;G09G5/06;G09G5/14;G09G5/36;G09G5/39;G09G5/395;(IPC1-7):G06F9/26;G06F9/34;G06F12/00 |
主分类号 |
G06F3/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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