| 摘要 |
The present invention relates to a new process for fabricating integrated circuits, and more particularly, to a CMOS IC process method of low cost, shallow junction and no crystal defects. After the gate oxide and gate electrodes have been formed on the N-well and the P-well, an N- Lightly-Doped-Drain (N- LDD) is made, then the sidewall of the N-channel polysilicon gate and the P-channel polysilicon gate are covered with dielectric spacer. A layer of PhosphoSilicate Glass (PSG) is thereafter deposited and patterned on the N-well and the pickup area of the P-well by lithography and etching techniques. Ion implantation is used to build the P+ Source/Drain (S/D) electrode, after which the sidewall spacer of the P-channel polysilicon gate is removed and a blanket implantation of P dopant forms the P- LDD on the area of the N-well. The P-well is doped with N-type dopant with its source from PSG by high temperature diffusing and forms the N+ S/D electrode.
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