| 摘要 |
The refresh circuit for refreshing the data stored at a cell array block of a DRAM device, has a refresh detector for detecting the refresh state; an internal address generator for receiving the output of the refresh detector and outputting an internal address signal during a refresh operation; an address memory for storing an address signal for a normal operation and comparing it with the output of the internal address generator; an address memory control signal generator for generating a signal for controlling the operation of the address memory by a ras signal, a cas signal and the signal output from the refresh detector; and an internal ras signal generator for outputting a signal for controlling the row path of the DRAM by the control of the ras signal, the cas signal and the output signal of the address memory.
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