| 摘要 |
This invention involves computing a mean squared error between a predetermined plural number of pairs of first and second values. A data processing apparatus (71, 72, 73, 74) has data registers (200), an arithmetic logic unit (230), a flags register (211), a multiplication unit (220), a source of instructions and an instruction decoder (245, 246, 250). The arithmetic logic unit (230) forms a difference between pairs. The flags register (211) stores status bits indicating whether the result is less than zero. The arithmetic logic unit (230) conditionally either adds the difference to zero if the status bit indicates the difference was not less than zero or subtracts the difference from zero if the status bit indicated the difference was less than zero. The multiplication unit (220) forms the square. The square is added to a running sum. The arithmetic logic unit can perform operations upon data in separate sections making plural simultaneous subtractions and forming plural status bits for corresponding sections. These plural status bits controls the absolute value function by conditional addition or subtraction of each section. The multiplication unit may also support multiplication by plural sections in a single data word. The plural products are added to respective running sums using sections of the arithmetic logic unit. The final separate running sums are added to form the general sum. In the preferred embodiment this invention is embodied in at least one digital image/graphics processor (71, 72, 73, 74) as a part of a multiprocessor (100) formed in a single integrated circuit used in image processing.
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