INTERFACE CIRCUIT FOR COMPRESSION IMAGE DECODER

摘要

PROBLEM TO BE SOLVED: To realize the circuit configuration that surely interfaces compression image data received continuously or in a burst form asynchronously with a compression image decode system clock with a compression image decoder at a low cost. SOLUTION: Compression image data 1402 and an enable signal 1403 synchronously with a communication clock 1401 are at first received by pre-stage data flip-flop circuits 2030, 2050 based on the communication clock 1401 and an edge of the communication clock used to receive the compression image data is detected based on the compression image decoding system block before succeeding compression image data are received. The compression image data are received by a post-stage data flip-flop 2040 by using it to realize the conversion of a compression image data rate at a high speed.