发明名称 |
Self-timed phase detector and method |
摘要 |
A self-timed phase detector for detecting the phase of an input signal, such as a high speed serial data stream. The self-timed phase detector includes a precharged latch, a phase detector circuit and a data valid gate. The precharged latch has a latch input, a sample clock input and first and second complementary latch outputs. The first and second complementary latch outputs have an active state and a precharged state. The phase detector circuit is coupled to the first latch output and generates a phase signal on a phase output as a function of the phase of the input signal. The data valid gate is coupled to the phase output for passing the phase signal when the latch outputs are in the active state and for blocking the phase signal when the latch outputs are in the precharged state.
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申请公布号 |
US5694062(A) |
申请公布日期 |
1997.12.02 |
申请号 |
US19960595854 |
申请日期 |
1996.02.02 |
申请人 |
LSI LOGIC CORPORATION |
发明人 |
WELCH, JAMES R.;MACTAGGART, IAIN ROSS;FIEDLER, ALAN |
分类号 |
H03K5/00;H03D13/00;H03L7/08;H03L7/089;H04L7/00;H04L7/033;(IPC1-7):H03P13/00 |
主分类号 |
H03K5/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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