| 摘要 |
A bit-serial digital expandor includes a bit-serial dual scaler block (340), a bit-serial lowpass wave digital filter block (350), a bit-serial scaler with overflow detection block (360), a bit-serial multiplier block (380), and a bit-serial scaler and clipper block (395). This bit-serial expandor can be used in an AMPS cellular telephone receiver to produce a receiver having a lower silicon area, gate count, and current drain compared to equivalent parallel architecture receivers.
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