发明名称 SAMPLE-AND-HOLD CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a sample-and-hold circuit in which feed through error voltage and offset error caused by a switch circuit is reduced. SOLUTION: Clock signalsϕ1,ϕ2 are made a high level, a clock signalϕ3 is made a low level, switch circuits 11, 14; 12, 15 are turned on, switch circuits 13, 16 are turned off, and input voltage V1, offset error voltage V0 are charged respectively to first and second capacitors 21, 22. Next, the clock signalsϕ1,ϕ2 are made a low level, the clock signalϕ3 is made high level, switch circuits 11, 14; 12, 15 are turned off, switch circuits 13, 16 are turned on, and offset error voltage V0 and feed through error voltage of the switch circuits are canceled.
申请公布号 JPH09306194(A) 申请公布日期 1997.11.28
申请号 JP19960120172 申请日期 1996.05.15
申请人 FUJI XEROX CO LTD 发明人 AZUMA KOICHI;YAMAGUCHI HIDEHIKO;TOMARI NAOSADA
分类号 G01R19/00;G11C27/02;H03M1/12;(IPC1-7):G11C27/02 主分类号 G01R19/00
代理机构 代理人
主权项
地址