| 摘要 |
<p>PROBLEM TO BE SOLVED: To improve the entire speed of variable length decoding processing. SOLUTION: A variable length code(VLC) decoding section 12 receives variable length coding information obtained by applying variable length coding to discrete cosine transformation(DCT) coefficient information of each block of image information and decodes the information in cooperation with a CPU 3. The decoded DCT coefficient information is sequentially stored along zigzag scanning to each assigned address of a memory 15 in the unit of blocks by a run level decoding section 14. A read circuit 16 reads a DCT coefficient in a prescribed sequence from the memory 15. When read data from the memory 15 are all '0' after that, a changeover device 17 is switched to read fixed data '0' from the read circuit 16 and the memory 15 is released till the read of all data is finished. A final address generating circuit 18 provides a switching timing of the changeover device 17 for the purpose.</p> |
