| 摘要 |
<p>PROBLEM TO BE SOLVED: To perform pre-charge of a bit line with low power consumption without reducing the data read-out speed by providing a pre-charge/column selection circuit instead of a column selection circuit. SOLUTION: An address transition detecting circuit(ATD circuit) 10 makes output level of both PC and SE signals a low level when an address signal AD changes. At this point a row decoding circuit 22 and a column decoding circuit 32 output a row selection signal and a column selection signal in accordance with AD, respectively. A pre-charge/column selection signal 35 makes the circuit operate so that only a bit line in which a logic product operation value of a column selection signal generated by the column decoding circuit 32 according to a column address and a PC signal generated by the ATD circuit 10 is made the prescribed value is pre-charged, and only one bit line out of 16 columns (C0-C15) is pre-charged. Consequently, since pre-charge is not performed for the remaining 15 bit lines being not selected, low power consumption can be realized.</p> |
