发明名称 ASYNCHRONIZING SIGNAL RECEPTION CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To simplify the shipping inspection of a product conducted after the manufacture without increasing kinds of referenced timing signals. SOLUTION: In the case that transmission data SD(1:0) and a transmission system synchronizing timing signal SCK are received by a synchronizing data update control circuit 42 in the same timing as a reception system synchronizing timing signal RCK, a delay signal LD2 is used to control a delay of the latter half of synchronizing transmission data DSD(1:0) thereby updating an output signal OUT(1:0). Furthermore, in the case that the reception system synchronizing timing signal RCK and the transmission data SD(1:0) are changed in the same timing after the change in the transmission system synchronizing timing signal SCK and that the transmission data SD(1:0) cannot be correctly received by the synchronizing data update control circuit 42 once for two periods of the reception system synchronizing timing signal RCK, the delay signal LD2 is used to select stably the synchronizing transmission data DSD(1:0) sampled by the reception system synchronizing timing signal RCK to update the output signal OUT(1:0).</p>
申请公布号 JPH09307594(A) 申请公布日期 1997.11.28
申请号 JP19960114811 申请日期 1996.05.09
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HORI SOJI
分类号 H04L25/40;H04L7/04;(IPC1-7):H04L25/40 主分类号 H04L25/40
代理机构 代理人
主权项
地址