发明名称 LAYOUT GRAPHIC CORRECTING METHOD
摘要 PROBLEM TO BE SOLVED: To shorten the time required for preparing a corrected graphic by generating a gap area graphic in the area between a selected side and polysilicon (PS), generating a completely corrected graphic in the case of correcting all sides of a gate graphic, and generating the corrected graphic from the combination of both the graphics. SOLUTION: In a step (S) 101, a diffusion layer is expanded with the distance of correction conditions as expansion quantity and the quantity of a PS layer is reduced. In S102, the deviation between the diffusion layer and the PS layer is defined as the expansion quantity and the layer is expanded. In S103, the overlap of the PS layer and the diffusion layer is found and a gate graphic is found. In S104, the 1st gap area graphic is generated by expanding and reducing the PS vertically to the respective sides. In S105, a square is moved with the surface of side of the PG layer graphic as a center and the 2nd gap area graphic for reducing its locus is generated. In oblique graphic selection processing 106, the graphic is divided into triangles and the graphic of an oblique side is selected. In S107, the 3rd gap area graphic is generated, in S108, the graphics are subtracted and in S109, the completely corrected graphic is generated.
申请公布号 JPH09305641(A) 申请公布日期 1997.11.28
申请号 JP19960117608 申请日期 1996.05.13
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 TSUZUKI KATSUO;SHIBATA HIDENORI
分类号 H01L21/82;G03F1/68;G03F1/70;G06F17/50 主分类号 H01L21/82
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