| 摘要 |
PROBLEM TO BE SOLVED: To conduct digital correction with a simple configuration by setting a correction value of a most significant bit, halving the correction value for each clock input and repeating further halving the halved value. SOLUTION: An object maximum value Pmax1 stored in a maximum value storage means 12 is inputted to a shift register 13, which shifts the bit location of the digital signal received as the maximum value Pmax1 by one bit each toward the lower-order bit direction every time a clock from a clock generator 16 is inputted so as to halve the maximum value Pmax1 and further halving of the halved value is repeated. That is, An accumulation means 14 is used to add the halved value to the input digital signal every time each bit of the input digital signal is logical 1 from the most significant bit and repeats the addition for number of times corresponding to the bit number of the input digital signal. Thus, the corrected digital value is obtained. |
