| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a semicustom semiconductor integrated circuit device in which the capacitance of the decoupling capacitor can be increased even if the number of pins on the gate array is increased and the pad area is reduced. SOLUTION: A semicustom semiconductor integrated circuit device is provided with multilayer wiring. A lower insulating layer 12 is formed in an unassigned bonding pad area on a substrate 11. A pattern of a lower wiring layer 13 is made on the lower insulating layer 11 and is covered by an intermediate insulting layer 14. A pattern of an intermediate layer 15 is made on the intermediate insulating layer 14 and is covered by an upper insulating layer 16. Further, a pattern of an upper wring layer 17 is made on the upper insulating lager 16 and is covered by a pasorvation layer 18. A power supply line VDD is connected to the lower wiring layer 13, a ground lien GND is connected to the intermediate layer 15, and another power supply line VDD is connected to the upper wiring layer 17 to constitute a decoupling capacitor.</p> |
