| 摘要 |
A logic circuit (2) converts signals, C=[Cn-1, Cn-2, ..., C1, C0] generated by a ring counter (1) into continuous triangular signals Q, in which the carrier frequency of PWM signals is the second power of the frequency of the signal C, and inputs the signal Q to the B-input of a magnitude comparator (3). On the other hand, the result of comparison, A > B, of the comparator (3) turns data D to be modulated held by a data holding circuit (4) into the PWM signals. The PMW signals are free from phase variation and high-resolution and low-pulsating-flow components. The resolution of the PWM signals per period of the counter (1) is maintained at n-bits and the carrier frequency of the PWM signals becomes the m<u>th</u> power of (2) of the frequency of the counter (1).
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