Electrostatic discharge protection device for CMOS integrated circuit

摘要

The device is part of a circuit to which an operational voltage, e.g. positive, is to be applied and it includes an SCR, incorporated between a circuit coupling fin and ground. A resistor, e.g. a JFET, is coupled to the coupling fin for the control of the SCR breakdown voltage. The resistor is controllable to high value, when the operational voltage is not applied. Thus the SCR is so controlled that it breaks down at a low electrostatic discharge voltage, lower than the circuit damaging voltage on operational voltage application to a low resistive value. The SCR is so controlled that it breaks down at an electrostatic discharge voltage higher than the low electrostatic discharge voltage.