Semiconductor chip memory repair comprises (a) severing interconnects at a defective normal memory cell for connecting a redundant memory cell instead of the normal cell and/or (b) forming an interconnect for connecting a redundant memory cell instead of a defective normal cell. The operation (a) involves coating the entire chip surface with a resist layer, exposing the resist layer with an energy (preferably electron) beam in the regions of the interconnects, developing the exposed resist layer to form a resist pattern and etching the chip to sever the interconnects using the resist pattern as mask. The operation (b) involves forming a resist pattern as above, etching the chip in the region for interconnect formation and depositing material to form the interconnect. The operation (b) may be carried out after operation (a) in a different region of the chip using the same resist layer. Also claimed are (i) an electron beam memory repair apparatus for carrying out the above process; and (ii) a redundancy memory circuit which can be repaired by the above process, the circuit having a redundant memory cell provided in a semiconductor chip and connected by an interconnect which branches from a data line of a normal memory cell and which has an interrupted region.
