SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE HAVING WRITE LATENCY CONTROL FUNCTION

摘要

A semiconductor memory device is provided which has a column address counter, burst length counter and data transmission switching circuit and processes data in synchronization with a system clock externally applied thereto. The semiconductor memory device includes means for generating a signal for controlling write latency, means for generating one active information expansion signal from a plurality of active information signals generated in response to a row-related control signal externally applied, and means for holding the inner operations of the column address counter, burst length counter and data transmission switching circuit for a predetermined period of time during which the active information expansion signal is in active state.