| 摘要 |
An input and output module for an array of processors is described. The module includes a first set of shift registers which transfers data words to and from a host for the processor array. A second set of shift registers is connected to the registers of the first set so that data can be shifted from the first set to the second set. The second set interfaces with the processor array. As a result, data may be loaded into the array by first loading the first set with data from the host, then shifting the data to the second set, and loading the data into the array. In the opposite operation, data is loaded from the array to the second set of shift registers and then transferred to the first set. Since the arrays may be clocked independently of each other, full duplex operation can be achieved. |
