| 摘要 |
<p>A fractional N-type PLL frequency synthesiser apparatus employs a control circuit for varying N values for different reference cycles, which is constructed of a combination of a frequency divider (comprising D flip-flops (45, 47)) and a logic circuit (comprising an exclusive OR circuit (46), AND circuits (48-50) and an OR circuit (52)), taking the timing provided to output a carry signal into consideration in advance. Owing to such a construction, the fractional N-type PLL frequency synthesiser apparatus can be activated with low noise and can provide a short lockup time. <IMAGE></p> |
