发明名称 |
Method and apparatus of redundancy for non-volatile memory integrated circuits |
摘要 |
<p>A redundancy circuit used in a non-volatile memory chip to increase the production yield due to manufacturing defects. The redundancy circuit includes a redundancy 'predecoder circuit, a source follower EEPROM (electrically erasable programmable read only memory) memory fuse, a scheme to use the column high voltage drivers (also known as page latch) to program the EEPROM fuses, a scheme to use the regular row decoder (also known as wordline driver or x-decoder) as the redundancy row decoder, and an out-of-bound address as a redundancy enable/disable signal.</p> |
申请公布号 |
EP0809186(A2) |
申请公布日期 |
1997.11.26 |
申请号 |
EP19970303385 |
申请日期 |
1997.05.19 |
申请人 |
INFORMATION STORAGE DEVICES, INC. |
发明人 |
VAN TRAN, HIEU;BLYTH, TREVOR |
分类号 |
G11C16/06;G11C16/04;G11C16/08;G11C27/00;G11C29/00;G11C29/04;(IPC1-7):G06F11/20 |
主分类号 |
G11C16/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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