| 摘要 |
<p>A burst frame phase synchronizing circuit is disclosed, whereby the generation of erroneous synchronization caused by the phase fluctuation of received data or a bit error. A transmission error monitoring circuit 15 monitors a transmission error and outputs error information and a transmission error statistical circuit 14 outputs protection information obtained by summing up the statistics of transmission errors. A frame synchronizing pattern comparator circuit 11 makes a comparison for bit strings between burst data at the time of transmission and a specified synchronizing pattern and outputs comparison information obtained based on the production state of a noncoincidence bit. A synchronization protective circuit 13 selects a permissible noncoincidence bit number and outputs a frame synchronizing signal satisfying a specified protection condition. Thus, since the strength of synchronization protection is flexibly switched according to a transmission line error, a synchronous bit length can be controlled without taking any unnecessarily strong synchronization protecting measures and transmission efficiency can be improved by controlling a frame synchronous bit length. <IMAGE></p> |
