| 摘要 |
A partial product generator in a binary multiplier for multiplying a parallel n-bit binary multiplier and a parallel m-bit binary multiplicand comprises n/2 (n being an even integer) or (n+1)/2 (n being an odd integer) number of Booth encoders, each of which generates a partial product and includes a first inverter for inverting a first two-bit extended, i.e., m+2 bits, multiplicand (ATO), a second inverter for inverting a second two-bit extended, i.e., m+2 bits, multiplicand (BTO), a first multiplexer for selecting one of the first and the second two-bit extended, inverted m+2 bit multiplicands, a plus "1" logic for adding a binary "1" to the m+2 bit binary number (CT) selected from the first multiplexer and a second multiplexer for selecting the first extended m+2 bit multiplicand, the second extended m+2 bit multiplicand or the added m+2 bit binary number, to thereby produce the partial product, wherein the selection operation of the first and the second multiplexers is controlled by a selection code derived from the n-bit multiplier.
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