发明名称 Circuit programmable de mémoire de codes pour mémoire flash.
摘要 <p>A flash memory device includes programmable code store circuitry stores algorithms used by an array controller to erase and program a nonvolatile main memory array, and includes a nonvolatile memory (100) for the algorithm instructions. The circuitry also includes support circuits, such as address multiplexer and decode circuitry (102-108), sense path circuitry (112), main array interface circuitry (110) and voltage generators (114-120). These circuits operate in several modes. In read mode, they ensure that the instructions in memory (100) are output to the array controller. In program and erase modes, the support circuits allow control of voltage level applied to the instruction memory, output of instruction data to user, and input of modified instructions to memory (100) via a page buffer (42). The support circuits are placed in the various modes via control signals output from control registers. Because these control registers are accessible to the device user, the user controls the mode in which the code store circuitry operates.</p>
申请公布号 FR2714513(B1) 申请公布日期 1997.11.21
申请号 FR19950001929 申请日期 1995.02.20
申请人 INTEL CORP 发明人 DURANTE RICHARD JOSEPH
分类号 G11C7/00;G11C16/06;(IPC1-7):G11C7/00 主分类号 G11C7/00
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