METHOD AND APPARATUS FOR PROVIDING USER SELECTABLE LOW POWER AND HIGH PERFORMANCE MEMORY ACCESS MODES

摘要

A data processing system (10) for providing memory access to a memory (18). The memory (18) includes a memory array (43) having a plurality of memory cells arranged in rows and columns and an address decoder (42) for accessing a memory cell (44) of the memory array (43) in response to decoding an address signal. Precharge logic (49) coupled to the memory array (43) and the address decoder (42) enables, in a high performance mode, all columns of the memory array (43) prior to accessing the memory cell (44). In a low power mode, the precharge logic (49) enables only selected columns of the memory array (43) prior to accessing the memory cell (44).