| 摘要 |
There is disclosed a DRAM emulation circuit for storing a parity, where the parity is used for detecting an error in a data transfer. A timing controller 70 receives a controlling signal RAS, CAS, and WE from a CPU, and generates and outputs writing and reading signals. A writing portion 60 receives a writing signal from the timing controller 70 and a reset signal from a power on reset portion 50, and outputs a writing signal only at a first writing operation. A register 10 receives writing and reset signals from the writing and reset portions 60 and 50, respectively, and stores first writing data d and data for input parity dpi. A first XOR 20 receives a data from the register 10 and generates a parity value. A second XOR 30 receives a data from a system memory and the output data of the first XOR 20, and generates a parity data. A three phase output portion 40 generates a parity data output dpo only when reading operation. The dram emulation circuit features that a low cost logic circuit emulates the function of a high cost DRAM in the prior art.
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