A novel metal wiring on a semiconductor component has: (a) an insulating layer formed on a lower metal wiring or an impurity diffusion region; (b) a contact plug embedded in the insulating layer and joined to the lower metal wiring or impurity diffusion region; (c) a first pattern layer buried in the insulating layer and in contact with the contact plug; and one or more second pattern layers in the form of islands on the inside of the first pattern layer. Also claimed is a process for producing a metal wiring on a semiconductor component by: (i) producing an insulating layer and a first etch-stop layer on a substrate; (ii) selectively removing these layers to form a first trench; (iii) producing a second etch-stop layer over the entire substrate surface and back-etching until the etch-stop layer remains only on the first trench side wall; (iv) isolating the insulating layer on the trench bottom using the first and second etch-stop layers as masks to produce a second narrower trench; and (v) removing the etch-stop layers to produce a contact plug and a buried conductive layer on the trenches.
