PROCESSOR WITH AN INSTRUCTION CACHE

摘要

An instruction cache has an input bus and an output bus, the input bus receiving bits of an instruction for storage in the instruction cache, the output bus comprising a set of parallel lines for outputting the bits of an instruction in parallel. To simplify the layout of the cache, the output order of the bits of the instruction on the set of parallel lines differs from a logical order of receiving the bits via the input bus. The bits of instruction words are shuffled prior to loading into the cache. Then when the words are read out of cache, the read lines need not cross.