| 摘要 |
Generator of clock pulses (CLK) having a period selectable between a first period, a second period of greater duration than that of the first period and a third period, with duration imposed by the transitions of a synchronization signal (SYNC) from a first to a second logic level, comprising: a resettable oscillator (1) controlled by a binary selection signal (SEL) having a first and second logic level, in order to generate periodic pulses (TOUT) having the first or second period depending on the logic level of the said selection signal, the oscillator comprising a pulse extractor (7) triggered by the periodic pulses (TOUT) and by the transitions from first to second logic level of the synchronization signal in order to generate, with each pulse and transition received as input, one of the said periodic clock pulses CLK, acting as reset signal for the oscillator, and a finite state logic machine, having at least two states A, B and inputs for receiving the synchronization signal (SYNC) and the periodic pulses (TOUT), and generating the selection signal (SEL) at a first logic level, in state A, and at the second logic level in state B, the machine evolving from state to state as a function of the signals SYNC and TOUT received as input. <IMAGE> |
