| 摘要 |
The data processing apparatus which outputs information regarding the prefetching of an instruction in the destination of a branch instruction prior to the confirmation of its branch condition. The apparatus uses the output information to delete unexecuted memory access from a trace memory so as to accurately trace the execution sequence of the apparatus by an incircuit emulator. Bus attribute information is output which indicates that the bus cycle under operation is an instruction fetch bus cycle in the destination of a branch instruction. Additionally, status information regarding a prefetched instruction in the destination of a branch instruction is used in order to invalidate the prefetched instruction.
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