发明名称 Method of fabricating a twin - well CMOS device
摘要 A method of fabricating a twin-well integrated circuit device to implant the dopants directly through the nitride layer including steps of: The pad oxide layer and nitride layer are formed on a P-type semiconductor silicon wafer. Then, the alignment mark photoresist pattern is formed by the conventional lithography technique, where the alignment mark region is in clear field, while other regions are in dark field. Next, the nitride layer is patterned by plasma-etching technique to form the nitride alignment mark. The N-well region is formed by lithography and ion-implantation techniques. Thereafter, the P-well region is formed by lithography and ion-implantation methods again. Next, the active device region photoresist is formed by lithography technique. The nitride layer is partially etched to open the windows by plasma-etching technique. The P-well region photoresist is then formed, followed by the deep-implantation process. The second P-well region photoresist is then formed, followed by the deep-implantation process. The field oxide regions for isolation are also grown in the window openings during the P-field drive-in step. Finally, the remaining of nitride layer is removed. This new process can reduce the number of processing steps so as to decrease the production cost.
申请公布号 US5688710(A) 申请公布日期 1997.11.18
申请号 US19960757179 申请日期 1996.11.27
申请人 HOLTEK MICROELECTRONICS, INC. 发明人 LU, BING-YAU
分类号 H01L21/8238;(IPC1-7):H01L27/00 主分类号 H01L21/8238
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