| 摘要 |
In the reverse sampling circuit, a counter(1) up-counts a set value to output an address signal. A ROM(2) outputs weight matrix data according to the address signal from the counter(1) in response to an intra/inter select signal. A multiplexor(3) selectively outputs one of intra weight matrix data, inter weight matrix data, or output data of the ROM(2) in response to a download signal and the intra/inter select signal. A weight matrix scan converter(4) zigzag stores the data from the multiplexor(3) and output the data in a form of a row. A count scan converter(5) stores counting data in the input order and zigzag reads the data. A reverse sampling device(6) receives the counting data from the count scan converter(5) and obtains reverse sampling data by a predetermined sampling formula.
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