| 摘要 |
A method and apparatus for providing low power management of a data processing system (FIG. 1) involves a CPU (12) communicating to a register file (16) in a processor (10). The CPU (12) communicates low power control and status values to/from the register file (16) via internal register file buses that are separate from internal data busses and address buses (22-26) which communicate with external data busses and address buses (34-38). The low power control and status values are stored in internal register (16a and 16b) which are coupled directly to external pins (52 and 54) of the processor (10). The registers (16a and 16b) are part of the user programming model of the processor (10). The low power information communicated between CPU (16), register (16a and 16b) and the pins (52 and 54) is communicated with little or no bandwidth problems and is efficient due to the separation from buses (22-26).
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