| 摘要 |
<p>PROBLEM TO BE SOLVED: To eliminate the need for register processing data '0' and to omit arithmetic operations of addition and multiplication for data '0' by integrating interpolation data '0' so as to be calculated by the same multiplier in an FIR digital filter circuit with (2n-1)-tap symmetrical around an odd number n-tap being 3 or over. SOLUTION: At the first operation, input data are given to an (n-1) read register group 2 via a selector 3, an (n-1)/2 read register group 1 and a selector 4. Then the selectors 3, 4 are thrown to the position of the output of the register groups 1, 2 respectively, the input and output of the register groups 1, 2 are connected to be a loop so as to conduct shift operation up to n-times. The obtained output data are added by an adder 5, a filter coefficient is multiplied with the sum and the results are accumulated by an accumulator 8. In this case, since the number of taps is an odd number, center data symmetrical to each other at a selector 6 are passed through the adder 5. Since data '0' are inserted at an interval of every other tap for interpolation and the data '0' appear odd number and even number taps repetitively, addition and multiplication to a same multiplier coefficient are omitted.</p> |
