| 摘要 |
PROBLEM TO BE SOLVED: To reduce packet assembly delay by putting the usage of an output line by starting the output successively from data having a large transmission quantity with a little circuit by transforming or assembling a packet through a two-dimensional memory shared by plural channels for the transmission data of plural channels. SOLUTION: By using a two-dimensional memory 3 for writing/reading data while designating column and row addresses, a memory control circuit 10 lets these respective columns respectively correspond to the respective plural channels. Under the address control of an input control circuit 4, the data of respective channels inputted from a data input line 1 are stored into the least significant row of column of the two-dimensional memory 3 corresponding to these channels. An output control circuit 5 simultaneously extracts data for one packet from the column stored in the respective columns of the two-dimensional memory 3, assembles the packet for each channel, adds a header to the packet through a header addition circuit 13 and performs the multiple output of that packet to a packet output line 2 in a time division manner. |
