| 摘要 |
<p>PURPOSE:To automatically select a retiming signal independently of the repeating frequency of an inputted data signal by constituting a circuit with a 1/3 frequency dividing circuit, a phase comparator and a selector. CONSTITUTION:A master clock signal 103 is subjected to 1/3 frequency division by a 1/3 frequency dividing circuit 107, from which 1/3 frequency division clock 1071-1073 (PHI0-PHI2) whose phase differs by 2pi/3 each are generated. When a phase comparator 108 decides that the change point of an output signal of a 1/2 frequency dividing circuit 106 is between the clock rises of the clock signals PHI0 and PHI1, the clock signal PHI2 is selected by a selector 109. Moreover, a latch circuit 111 applies retiming to the output signal of a latch circuit 110 in the timing of the output signal of the selector 109 without error, an data signals 1121-1123 synchronously with the phase of the master clock signal are outputted. Thus, the retiming signal is selected automatically independently of the repeating frequency of the inputting data.</p> |
