| 摘要 |
<p>The present invention relates to an arrangement and a method respectively for instruction processing comprising a multi-stage pipeline arrangement (13A, 13B; 23A, 23B; 33) to which instructions are delivered from at least one instruction source (PS) (11; 21; 31) and a storing arrangement (14A, 14B; 24A, 24B; 25A, 25B; 34) for storing jump address information for jump instructions. The storing arrangement (14A, 14B; 24A, 24B; 25A, 25B; 34) comprises at least one FIFO-register. The conditional jump target address information is stored in said at least one FIFO-register (14A, 14B; 24A, 24B; 25A, 25B; 34) while at least the jump instructions are stored in said pipeline arrangement (13A, 13B; 23A, 23B; 33), and the jump target address information is delivered from said at lest one FIFO-register, in such a way that substantially sequential and continuous prefetching of the instructions is enabled irrespective of the number of conditional jumps and irrespective of whether the jumps are taken or not.</p> |
