A filter circuit for use in providing a compressed digital signal with reduced aliasing comprises a finite impulse response filter (10-15 and 17) arranged to read sets of data samples corresponding to pixels of a video image from a store 11 and to sum weighted samples to provide a first stage filter output signal (18). A second stage of the filter comprises a mixer (19) a latch (22) and a selector circuit (24). The mixer (19) receives the first stage output signal 18 and provides to the latch (22) a mixed signal comprising proportions of the input signal (18) and a signal previously stored in the latch (22). From a sequence of signals determined by a logic unit (16) a single output signal is selected by the selector unit (24) to provide a signal representing the required compression of the sequence of signals derived from the image store (11). <IMAGE>
