发明名称 |
Paritätsprüfungsschaltung für Speicher mit doppelter Gültigkeitsanzeige |
摘要 |
A memory which is cleared by simultaneously clearing a special bit in each entry within the memory, an extra bit, used for other purposes, is also cleared. When both bits have a value of 0, parity checking is disabled. When either bit has a value of 1, parity checking is enabled. This prevents incorrect detection of parity errors after the memory device has been cleared. <IMAGE> |
申请公布号 |
DE69222554(D1) |
申请公布日期 |
1997.11.13 |
申请号 |
DE1992622554 |
申请日期 |
1992.03.27 |
申请人 |
SGS-THOMSON MICROELECTRONICS, INC., CARROLLTON, TEX., US |
发明人 |
RASTEGAR, BAHADOR, DALLAS, TEXAS 753821, US |
分类号 |
G06F11/10;G06F12/08;G06F12/16;(IPC1-7):G06F11/10;G06F11/08 |
主分类号 |
G06F11/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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