Data processing circuit structure for describing or modelling of digital circuit

摘要

The circuit for processing several data streams including functional units for carrying out a number of logic or arithmetic basic functions (1e,2e,3e) i.e. ALUs, a digital information store (RAM), (7), clocked registers (6,8) giving stepped status exchange. One ALU (3c) is assigned per data stream (3) and is specially designed for a particular processing task (11-15) and generates the control (11,131,4) data and the input (12;14) data for the RAM (7) or the register (6), with control (6a) or RAM- or register output data (9,10) feedback to the assigned ALU (3c). At least two ALUs (1e,2e,3e) are provided for the data streams (1,2,3) when one ALU function cannot be separated into several ALUs as described.