SYSTEM AND METHOD FOR HIGH-SPEED SKEW-INSENSITIVE MULTI-CHANNEL DATA TRANSMISSION

摘要

A method and apparatus is disclosed that receives a multi-channel digital serial encoded signal and converting it into a synchronized set of binary characters. A charge pump phase-locked loop receives a transmitted reference clock and derives a multi-phase clock from the reference clock. The multi-phase clock is used to control a plurality of multi-bit block assembly circuits. Each assembly circuit receives one channel of the digital signal and produces a multi-bit block or character. The multi-bit block assembly circuit includes an oversampler, a digital phas e- locked loop and a byte synchronizer. The oversampler oversamples the received digit al signal under control of the multi-phase clock and produces a sequence of oversampled binary data. The digital phase-locked loop receives the oversampled data and selects samples from it depending on the skew characteristics of the sample. The byt e synchronizer assembles a sequence of selected bits into a bit block, or character. An interchannel synchronizer receives as input the characters produced by each of the multi-bit block assembly circuits, and selectively delays output of the received characters in order to synchronize the characters of each channel with one another.