STORAGE CELL ARRANGEMENT IN WHICH VERTICAL MOS TRANSISTORS HAVE AT LEAST THREE DIFFERENT THRESHOLD VOLTAGES DEPENDING ON STORED DATA, AND METHOD OF PRODUCING SAID ARRANGEMENT

摘要

In a storage cell arrangement which comprises vertical MOS transistors as storage cells, the data are stored by at least three different threshold voltage values of the transistors by means of multi-level programming. One threshold voltage value is produced by the thickness of the gate dielectric in the sense of a thick oxide transistor and the other threshold voltage values are produced by different channel dopings. The arrangement can be produced with a surface area requirement per storage cell of 2 F<2> (F: minimum structural size).