| 摘要 |
<p>A digital to analogue converter having a plurality of output stages (46). Each output stage (46) includes a tri-state buffer (54) that outputs an on-signal, an off-signal or a pulse width modulated signal PWM that is selected by a multiplexer (52) that operates under control of a chord decoder (50) that is responsive to exponent bits within the input digital signal value. If a pulse width modulated signal is selected, then its duty cycle is controlled by a pulse width modulated decoder (48) that is responsive to mantissa bits within the input digital signal value. A further output provides a pulse width modulated signal of a predetermined duty cycle that may be used as a reference signal to compensate for variations in the operation of the rest of the digital to analogue circuit.</p> |
