| 摘要 |
<p>A circuit arrangement protects an FET power switch against damage from short circuits that may occur in the load connected between the drain terminal and an operating voltage source of the FET. The protection is achieved by the cooperation between a shunt resistor (3) connected between ground and the source terminal (S) of the FET and a gate voltage limiter (7) connected to the gate terminal of the FET. This cooperation limits the short circuit current through the FET until a short circuit detector (DT) provides a control signal that switches the FET off.</p> |
